11402 工程學群 半導體學院

設計自動化一 ing

李炯霆 教授

半導體學院

 

國立清華大學半導體研究學院 特聘教授
美國加州大學柏克萊分校電子工程博士
 【 人生理念 】長年致力於EDA電子設計自動化領域並有優異表現,
 始終為複雜的晶片設計挑戰提供具影響力的解決方案。
 【 教學網站 】https://reurl.cc/DbMn36
 https://reurl.cc/Zldab3
 【 研究專長 】專長於 3DIC 佈局設計、RC 寄生參數分析與除錯,以及精準的客製化佈局。
 ☉ 3DIC layout, RC parasitic analysis/debugging, custom layout
 【 教學領域 】設計自動化一二  Design automation (Ⅰ) (Ⅱ)
 機器學習與設計自動化 Machine Learning in EDA
 領導統御 Leadership
 企業領導 Executive Leadership
  

 

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最新公告

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Syllabus

課程大綱

在進入這堂課程選讀之前,請先裝備好你的新手大禮包
 邏輯設計的盾、資料結構的劍,還有電晶體的小知識!備齊裝備,我們就出發!
 ♠ 邏輯設計與資料結構(及基本電晶體設計)
   logic design & data structures (& basic transistor design)

 

 

指定用書
Required Textbook 

S. H. Gerez , Algorithms for VLSI Design Automation , John Wiley & Sons, 1999
W. Chang, K. T. Cheng, L. T. Wang (editors): Electronic Design Automation: Synthesis,
 Verification, and Test Elservier , 2009
 〡雖無新版,但該書完整涵蓋從 ESL 到實體設計的 EDA 全流程,仍是專家眼中最具價值的經典教科書
  

   

 

課程簡述
Brief course description

 
 清華大學半導體研究學院特聘教授李炯霆,憑藉曾任新思科技(Synopsys)副總裁及思源科技(SpringSoft)研發副總的資深資歷,深植其在 EDA 領域的領袖地位。李教授專精於「設計自動化」實務教學,核心授課範疇橫跨 EDA 演算法及 3DIC 精密佈局技術;李教授將分享多年 EDA 工具開發經驗,期盼藉由教學串連產學,縮減理論與實務的距離。
 Jeong-Tyng Li, NTHU Distinguished Professor and former Vice President of Synopsys, is a leading authority in the EDA industry. His expertise spans EDA algorithms and 3DIC layout, with a curriculum focused on practical design automation. By integrating foresight in AI chip design and logic synthesis into his teaching, By integrating his experience in leading several EDA tool development into his teaching, Professor Li acts as a strategic link between industry and academia, effectively narrowing the gap between theoretical research and industrial practice.
  

課程目標
Course Objectives

 Understand what EDA is all about very broad area
 Many important algorithms used in EDA tools are explained
 Learn problem formulation and solving
 Motivate interests (this semester is more for digital SOC design)
  Many software talents are needed in EDA
 Have fun
 Please utilize me (even off campus)
 

 

課程大綱
Course Outline

 Introduction to EDA; Technology nodes; Basic CMOS design (1 week)
 Physical design: compaction, floorplan, placement, routing (6 week)
  Gordian placer example
 Mid term quiz (in 2 nd half of April)
 Timing, delay calculation, clock tree synthesis, simulation (2 week)
 Logic synthesis, optimization, technology mapping (2 weeks)
 Program demo/presentation (1 weeks)
 Design rules, nanometer design (if we have time)
This semester is more for digital design; But testing is not covered.
In general, if you are interested in studying EDA area, welcome to talk to me.
 本學期的重點側重於數位設計,暫不涵蓋測試領域。
總體而言,若你對 EDA(電子設計自動化)領域感興趣,歡迎來找我面談。

 

 

評分標準
Grading
〡Information current as of January 15, 2026.

18 %homework
 〡Discussion encouraged, but solutions are written down separately (i.e., individual work)
  Likely 3 assignments
60 %programs & demo/presentation (team work of <=2 persons)
 Likely 4 programs, including a global router
15 %mid term quiz (open notes)
7 %for class participation (e.g., asking questions, demo, helping, …)
  Note : final grade is based on grading on a curve !
                             最終成績將採相對分數(常模參照)評定 !

 



Keyword

關鍵字

  • 演算法 (algorithms)
  • 佈局 (placement)
  • 路由 (routing)
  • 邏輯合成 (logic optimization)
  • 技術映射 (technology mapping)