開放式課程>>工程學群>>數位邏輯設計>>第11講 Registers and Counters

第11講 Registers and Counters

 

L11A
      Registers and Register Transfer

L11B
      Parallel Adder with Accumulator

L11C
      Shift Registers

L11D
      Design of a Binary Counter

L11E
      Design of a Binary Counter - Up-down Counter

L11F
      Design of a Binary Counter - Loadable Counter with Count Enable

L11G
      Counters for Other Sequences - T Flip-Flop

L11H
      Counters for Other Sequences - D Flip-Flop, S-R Flip-Flop, J-K Flip-Flop

 

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